1. Field of the Invention
The present invention relates to a semiconductor device including a floating gate nonvolatile storage element.
2. Description of Related Art
An EEPROM (Electrically Erasable Programmable Read Only Memory) is known as a typical nonvolatile memory.
FIG. 13 is a schematic plan view of a conventional EEPROM. FIG. 14 is a schematic sectional view of the EEPROM taken along a line XIII-XIII in FIG. 13.
An EEPROM 121 includes a plurality of memory cells arrayed in the form of a matrix in a direction X and a direction Y orthogonal thereto. Each memory cell includes an N-type first diffusion region, an N-type second diffusion region 124 and an N-type third diffusion region 125 formed in the surface layer portion of a P-type silicon substrate 122 at intervals in the direction x. A first insulating film is laminated on the silicon substrate 122. Each memory cell further includes a floating gate 126 and a select gate 127 formed on the first insulating film. The floating gate 126 is formed to extend over the first diffusion region 123 and the second diffusion region 124 in plan view. A control gate 129 is provided on the floating gate 126 through a second insulating film 128. The control gate 129 is formed to cover the upper surface and the side surfaces of the floating gate 126. On a position where the second diffusion region 124 and the floating gate 126 are opposed to each other, the first insulating film is partially removed, and then a tunnel window (a tunnel insulating film) 130 generally rectangular in plan view is formed at the removed portion. The tunnel window 130 is thinner than the first insulating film. On the other hand, the select gate 127 is formed to extend over the second diffusion region 124 and the third diffusion region 125 in plan view.
Thus, each memory cell has a memory transistor consisting of the first diffusion region 123, the second diffusion region 124, the first insulating film, the floating gate 126, the second insulating film 128 and the control gate 129. Further, each memory cell has a select transistor consisting of the second diffusion region 124, the third diffusion region 125, the first insulating film and the select gate 127.
A bit line 131 extending in the direction X is provided above the control gate 129 through an inter layer dielectric film. The bit line 131 is connected to the third diffusion regions 125 (drain regions of the select transistors) of the memory cells arrayed in the direction X under the same through contact plugs 132. The control gates 129 of the memory cells arrayed in the direction Y are integrated into a word line extending in the direction Y. The select gates 127 of the memory cells arrayed in the direction Y are integrated into a select line extending in the direction Y. The first diffusion regions 123 (source regions of the memory transistors) of the memory cells arrayed in the direction Y are integrated into a source line extending in the direction Y.
Referring to FIGS. 13 and 14, illustration of the first insulating film and the inter layer dielectric film is omitted.
As shown in FIG. 13, each pair of memory cells adjacent to each other in the direction X have symmetrical structures with respect to a straight line extending there between in the direction Y. The first diffusion region 123 is shared by the memory cells provided on both sides of the first diffusion region 123 in the direction X as the source regions of the memory transistors. Thus, the cell size (the area of each memory cell) is reduced.
However, further increase in capacity and downsizing are required to a nonvolatile memory such as an EEPROM, and the cell size must be further reduced in order to satisfy the requirements.